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application note ds038 (v1.3) october 9, 2000 www.xilinx.com 1 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. features ? industry's first totalcmos? pld - both cmos design and process technologies fast zero power (fzp?) design technique provides ultra-low power and very high speed high speed pin-to-pin delays of 8ns ultra-low static power of less than 35 a 100% routable with 100% utilization while all pins and all macrocells are fixed deterministic timing model that is extremely simple to use two clocks available programmable clock polarity at every macrocell support for asynchronous clocking innovative xpla? architecture combines high speed with extreme flexibility 1000 erase/program cycles guaranteed 20 years data retention guaranteed logic expandable to 37 product terms pci compliant advanced 0.5 e 2 cmos process security bit prevents unauthorized access design entry and verification using industry standard and xilinx cae tools reprogrammable using industry standard device programmers innovative control term structure provides either sum terms or product terms in each logic block for: - programmable 3-state buffer - asynchronous macrocell register preset/reset programmable global 3-state pin facilitates ?bed of nails' testing without using logic resources available in both plcc and vqfp packages description the xcr3032 cpld (complex programmable logic device) is the first in a family of coolrunner ? cplds from xilinx. these devices combine high speed and zero power in a 32 macrocell cpld. with the fzp design technique, the xcr3032 offers true pin-to-pin speeds of 8 ns, while simultaneously delivering power that is less than 35 a at standby without the need for ? turbo bits ? or other power down schemes. by replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in plds since the bipolar era) with a cas- caded chain of pure cmos gates, the dynamic power is also substantially lower than any competing cpld. these devices are the first totalcmos plds, as they use both a cmos process technology and the patented full cmos fzp design technique. for 5v applications, xilinx also offers the high speed xcr5032 cpld that offers pin-to-pin speeds of 6 ns. the xilinx fzp cplds utilize the patented xpla (extended programmable logic array) architecture. the xpla architecture combines the best features of both pla and pal type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. the xpla structure in each logic block provides a fast 8 ns pal path with five ded- icated product terms per output. this pal path is joined by an additional pla structure that deploys a pool of 32 prod- uct terms to a fully programmable or array that can allo- cate the pla product terms to any output in the logic block. this combination allows logic to be allocated efficiently throughout the logic block and supports as many as 37 product terms on an output. the speed with which logic is allocated from the pla array to an output is only 2.5 ns, regardless of the number of pla product terms used, which results in worst case t pd 's of only 10.5 ns from any pin to any other pin. in addition, logic that is common to multiple outputs can be placed on a single pla product term and shared across multiple outputs via the or array, effectively increasing design density. the xcr3032 cplds are supported by industry standard cae tools (cadence/orcad, exemplar logic, mentor, synopsys, synario, viewlogic, and synplicity), using text (abel, vhdl, verilog) and/or schematic entry. design ver- ification uses industry standard simulators for functional and timing simulation. development is supported on per- sonal computer, sparc, and hp platforms. device fitting uses a xilinx developed tool, xpla professional (available on the xilinx web site). the xcr3032 cpld is reprogrammable using industry standard device programmers from vendors such as data i/o, bp microsystems, sms, and others. 0 xcr3032: 32 macrocell cpld ds038 (v1.3) october 9, 2000 0 14* product specification r xcr3032.fm page 1 monday, october 9, 2000 6:44 pm
r xcr3032: 32 macrocell cpld ds038 (v1.3) october 9, 2000 www.xilinx.com 2 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. xpla architecture figure 1 shows a high level block diagram of a 32 macro- cell device implementing the xpla architecture. the xpla architecture consists of logic blocks that are interconnected by a zero-power interconnect array (zia). the zia is a vir- tual crosspoint switch. each logic block is essentially a 36v16 device with 36 inputs from the zia and 16 macro- cells. each logic block also provides 32 zia feedback paths from the macrocells and i/o pins. from this point of view, this architecture looks like many other cpld architectures. what makes the coolrunner family unique is what is inside each logic block and the design technique used to implement these logic blocks. the contents of the logic block will be described next. logic block architecture figure 3 illustrates the logic block architecture. each logic block contains control terms, a pal array, a pla array, and 16 macrocells. the six control terms can individually be configured as either sum or product terms, and are used to control the preset/reset and output enables of the 16 macrocells ? flip-flops. the pal array consists of a pro- grammable and array with a fixed or array, while the pla array consists of a programmable and array with a pro- grammable or array. the pal array provides a high speed path through the array, while the pla array provides increased product term density. each macrocell has five dedicated product terms from the pal array. the pin-to-pin t pd of the xcr3032 device through the pal array is 8 ns. if a macrocell needs more than five product terms, it simply gets the additional product terms from the pla array. the pla array consists of 32 product terms, which are available for use by all 16 macro- cells. the additional propagation delay incurred by a mac- rocell using one or all 32 pla product terms is just 2.5 ns. so the total pin-to-pin t pd for the xcr3032 using six to 37 product terms is 10.5 ns (8 ns for the pal + 2.5 ns for the pla). figure 1: xilinx xpla cpld architecture logic block i/o 36 16 16 36 16 16 mc1 mc2 mc16 i/o mc1 mc2 mc16 sp00439 zia logic block logic block i/o 36 16 16 mc1 mc2 mc16 36 16 16 i/o mc1 mc2 mc16 logic block xcr3032.fm page 2 monday, october 9, 2000 6:44 pm
r xcr3032: 32 macrocell cpld 3 www.xilinx.com ds038 (v1.3) october 9, 2000 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. figure 2: xilinx xpla logic block architecture to 16 macrocells 6 5 control pal array 36 zia inputs pla array (32) sp00435a xcr3032.fm page 3 monday, october 9, 2000 6:44 pm
r xcr3032: 32 macrocell cpld ds038 (v1.3) october 9, 2000 www.xilinx.com 4 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. macrocell architecture figure 3 shows the architecture of the macrocell used in the coolrunner family. the macrocell consists of a flip-flop that can be configured as either a d- or t-type. a d-type flip-flop is generally more useful for implementing state machines and data buffering. a t-type flip-flop is generally more useful in implementing counters. all coolrunner ? family members provide both synchronous and asynchro- nous clocking and provide the ability to clock off either the falling or rising edges of these clocks. these devices are designed such that the skew between the rising and falling edges of a clock are minimized for clocking integrity. there are two clocks (clk0 and clk1) available on the xcr3032 device. clock 0 (clk0) is designated as the "synchronous" clock and must be driven by an external source. clock 1 (clk1) can either be used as a synchro- nous clock (driven by an external source) or as an asyn- chronous clock (driven by a macrocell equation). the timing for asynchronous clocks is different in that the t co time is extended by the amount of time that it takes for the signal to propagate through the array and reach the clock network, and the t su time is reduced. two of the control terms (ct0 and ct1) are used to control the preset/reset of the macrocell's flip-flop. the pre- set/reset feature for each macrocell can also be disabled. note that the power-on reset leaves all macrocells in the "zero" state when power is properly applied. the other four control terms (ct2-ct5) can be used to control the output enable of the macrocell's output buffers. the reason there are as many control terms dedicated for the output enable of the macrocell is to insure that all coolrunner devices are pci compliant. the macrocell's output buffers can also be always enabled or disabled. all coolrunner devices also provide a global 3-state (gts) pin, which, when enabled and pulled low, will 3-state all the outputs of the device. this pin is provided to support "in-circuit testing" or "bed-of-nails ? testing. there are two feedback paths to the zia: one from the macrocell, and one from the i/o pin. the zia feedback path before the output buffer is the macrocell feedback path, while the zia feedback path after the output buffer is the i/o pin zia path. when the macrocell is used as an output, the output buffer is enabled, and the macrocell feedback path can be used to feedback the logic implemented in the mac- rocell. when the i/o pin is used as an input, the output buffer will be 3-stated and the input signal will be fed into the zia via the i/o feedback path, and the logic imple- mented in the buried macrocell can be fed back to the zia via the macrocell feedback path. it should be noted that unused inputs or i/os should be properly terminated. terminations the coolrunner xcr3032 cplds are totalcmos devices. as with other cmos devices, it is important to consider how to properly terminate unused inputs and i/o pins when fabricating a pc board. the xcr3032 devices do not have on-chip termination circuits, so it is recom- mended that unused inputs and i/o pins be properly termi- nated. allowing unused inputs and i/o pins to float can cause the voltage to be in the linear region of the cmos input structures, which can increase the power consump- tion of the device. xilinx recommends the use of 10k ? pull-up resistors for the termination. using pull-up resistors allows the flexibility of using these pins should late design changes require additional i/o. these unused pins may also be tied directly to v cc , but this will make it more diffi- cult to reclaim the use of the pin, should this be needed by a subsequent design revision. see the application note te r- minating unused i/o pins in xilinx xpla1 and xpla2 coolrunner cplds for more information. figure 3: xcr3032 macrocell architecture ct2 ct3 ct4 ct5 v cc gnd init (p or r) d/t q sp00440 clk0 pa l pla clk0 clk1 clk1 t o zia gnd ct0 ct1 gnd gts xcr3032.fm page 4 monday, october 9, 2000 6:44 pm
r xcr3032: 32 macrocell cpld 5 www.xilinx.com ds038 (v1.3) october 9, 2000 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. simple timing model figure 5 shows the coolrunner timing model. the cool- runner timing model looks very much like a 22v10 timing model in that there are three main timing parameters, including t pd , t su , and t co . in other architectures, the user may be able to fit the design into the cpld, but is not sure whether system timing requirements can be met until after the design has been fit into the device. this is because the timing models of competing architectures are very complex and include such things as timing dependencies on the number of parallel expanders borrowed, sharable expand- ers, varying number of x and y routing channels used, etc. in the xpla architecture, the user knows up front whether the design will meet system timing requirements. this is due to the simplicity of the timing model. for example, in the xcr3032 device, the user knows up front that if a given output uses five product terms or less, the t pd = 8 ns, the t su = 6.5 ns, and the t co = 7.5 ns. if an output is using six to 37 product terms, an additional 2.5 ns must be added to the t pd and t su timing parameters to account for the time to propagate through the pla array. totalcmos design technique for fast zero power xilinx is the first to offer a totalcmos cpld, both in pro- cess technology and design technique. xilinx employs a cascade of cmos gates to implement its sum of products instead of the traditional sense amp approach. this cmos gate implementation allows xilinx to offer cplds which are both high performance and low power, breaking the para- digm that to have low power, you must have low perfor- mance. refer to figure 6 and tab le 1 showing the i cc vs. frequency of our xcr3032 totalcmos cpld. figure 4: coolrunner timing model output pin input pin sp00441 t pd_pal = combinatorial pal only t pd_pla = combinatorial pal + pla output pin input pin dq registered t su_pal = pal only t su_pla = pal + pla registered t co global clock pin xcr3032.fm page 5 monday, october 9, 2000 6:44 pm
r xcr3032: 32 macrocell cpld ds038 (v1.3) october 9, 2000 www.xilinx.com 6 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. figure 5: i cc vs. frequency at v cc = 3.3v, 25c table 1: i cc vs. frequency (v cc = 3.3v, 25 c ) frequency (mhz) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 typical i cc (ma) 0.01 2.37 4.65 6.80 9.06 11.1 13.5 15.5 17.4 20.0 22.1 24.4 26.6 28.5 0 5 10 15 20 25 30 10 20 30 40 50 60 70 80 90 100 110 120 130 typical i cc (ma) frequency (mhz) sp00443 1 xcr3032.fm page 6 monday, october 9, 2000 6:44 pm
r xcr3032: 32 macrocell cpld 7 www.xilinx.com ds038 (v1.3) october 9, 2000 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. absolute maximum ratings 1 operating range symbol parameter min. max. unit v cc supply voltage 2 -0.5 7.0 v v i input voltage -1.2 v cc +0.5 v v out output voltage -0.5 v cc +0.5 v i in input current -30 30 ma i out output current -100 100 ma t j maximum junction temperature -40 150 c t str storage temperature -65 150 c notes: 1. stresses above those listed may cause malfunction or permanent damage to the device. this is a stress rating only. functional operation at these or any other condition above those indicated in the operational and programming specification is not implied. 2. the chip supply voltage must be monotonic. product grade temperature voltage commercial 0 to +70 c3.3v 10% industrial -40 to +85 c3.3v 10% xcr3032.fm page 7 monday, october 9, 2000 6:44 pm
r xcr3032: 32 macrocell cpld ds038 (v1.3) october 9, 2000 www.xilinx.com 8 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. dc electrical characteristics for commercial grade devices commercial: 0 c t amb +70 c; 3.0v v cc 3.6v symbol parameter test conditions min. max. unit v il input voltage low v cc = 3.0v 0.8 v v ih input voltage high v cc = 3.6v 2.0 v v i input clamp voltage v cc = 3.0v, i in = -18 ma -1.2 v v ol output voltage low v cc = 3.0v, i ol = 8 ma 0.5 v v oh output voltage high v cc = 3.0v, i oh = -8 ma 2.4 v i il input leakage current low v cc = 3.6v (except cko), v in = 0v -10 10 a i ih input leakage current high v cc = 3.6v, v in = 3.0v -10 10 a i il clock input leakage current v cc = 3.6v, v in = 0.4v -10 10 a i ozl 3-stated output leakage current low v cc = 3.6v, v in = 0.4v -10 10 a i ozh 3-stated output leakage current high v cc = 3.6v, v in = 3.0v -10 10 a i ccq 1 standby current v cc = 3.6v, t amb = 0 c 35 a i ccd 1, 2 dynamic current v cc = 3.6v, t amb = 0 c at 1 mhz 0.5 ma v cc = 3.6v, t amb = 0 c at 50 mhz 18 ma i os short circuit output current 3 one pin at a time for no longer than 1 second -5 -100 ma c in input pin capacitance 3 t amb = 25 c, f = 1 mhz 8pf c clk clock input capacitance 3 t amb = 25 c, f = 1 mhz 512pf c i/o i/o pin capacitance 3 t amb = 25 c, f = 1 mhz 10 pf notes: 1. see table 1 on page 6 for typical values. 2. this parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded. inputs are tied to v cc or ground. this parameter guaranteed by design and characterization, not testing. 3. typical values, not tested. xcr3032.fm page 8 monday, october 9, 2000 6:44 pm
r xcr3032: 32 macrocell cpld 9 www.xilinx.com ds038 (v1.3) october 9, 2000 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. ac electrical characteristics 1 for commercial grade devices commercial: 0 c t amb + 70 c; 3.0v v cc 3.6v symbol parameter 81012 unit min. max. min. max. min. max. t pd_pal propagation delay time, input (or feedback node) to output through pal 2 8 210212ns t pd_pla propagation delay time, input (or feedback node) to output through pal + pla 3 10.5 3 13 3 15 ns t co clock to out (global synchronous clock from pin) 2 7 2 9 2 11 ns t su_pal setup time (from input or feedback node) through pal 6.5 8.5 10.5 ns t su_pla setup time (from input or feedback node) through pal + pla 9 11.5 13.5 ns t h hold time 000ns t ch clock high time 3 4 5 ns t cl clock low time 3 4 5 ns t r input rise time 20 20 20 ns t f input fall time 20 20 20 ns f max1 maximum ff toggle rate 2 (1/t ch + t cl ) 167 125 100 mhz f max2 maximum internal frequency 2 (1/t supal + t cf ) 836350mhz f max3 maximum external frequency 2 (1/t supal + t co ) 745747mhz t buf output buffer delay time 1.5 1.5 1.5 ns t pdf_pal input (or feedback node) to internal feedback node delay time through pal 6.5 8.5 10.5 ns t pdf_pla input (or feedback node) to internal feedback node delay time through pal + pla 9 11.5 13.5 ns t cf clock to internal feedback node delay time 5.5 7.5 9.5 ns t init delay from valid v cc to valid reset 50 50 50 s t er input to output disable 3 15 17 19 ns t ea input to output valid 15 17 19 ns t rp input to register preset 16 18 20 ns t rr input to register reset 19 21 23 ns notes: 1. specifications measured with one output switching. see figure 6 and table 2 for derating. 2 . this parameter guaranteed by design and characterization, not by test. 3. output c l = 5 pf. xcr3032.fm page 9 monday, october 9, 2000 6:44 pm
r xcr3032: 32 macrocell cpld ds038 (v1.3) october 9, 2000 www.xilinx.com 10 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. dc electrical characteristics for industrial grade devices industrial: -40 c t amb +85 c; 3.0v v cc 3.6v symbol parameter test conditions min. max. unit v il input voltage low v cc = 3.0v 0.8 v v ih input voltage high v cc = 3.6v 2.0 v v i input clamp voltage v cc = 3.0v, i in = -18 ma -1.2 v v ol output voltage low v cc = 3.0v, i ol = 8 ma 0.5 v v oh output voltage high v cc = 3.0v, i oh = -8 ma 2.4 v i il input leakage current low v cc = 3.6v (except cko), v in = 0.4v -10 10 a i ih input leakage current high v cc = 3.6v, v in = 3.0v -10 10 a i il clock input leakage current v cc = 3.6v, v in = 0.4v -10 10 a i ozl 3-stated output leakage current low v cc = 3.6v, v in = 0.4v -10 10 a i ozh 3-stated output leakage current high v cc = 3.6v, v in = 3.0v -10 10 a i ccq 1 standby current v cc = 3.6v, t amb = -40 c45 a i ccd 1, 2 dynamic current v cc = 3.6v, t amb = -40 c at 1 mhz 0.5 ma v cc = 3.6v, t amb = -40 c at 50 mhz 18 ma i os short circuit output current 3 one pin at a time for no longer than 1 second -5 -120 ma c in input pin capacitance 3 t amb = 25 c, f = 1 mhz 8 pf c clk clock input capacitance 3 t amb = 25 c, f = 1 mhz 5 12 pf c i/o i/o pin capacitance 3 t amb = 25 c, f = 1 mhz 10 pf notes: 1. see table 1 on page 6 for typical values. 2. this parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded. inputs are tied to v cc or ground. this parameter guaranteed by design and characterization, not testing. 3. typical values, not tested. xcr3032.fm page 10 monday, october 9, 2000 6:44 pm
r xcr3032: 32 macrocell cpld 11 www.xilinx.com ds038 (v1.3) october 9, 2000 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. ac electrical characteristics 1 for industrial grade devices industrial: -40 c t amb +85 c; 3.0v v cc 3.6v symbol parameter 10 12 unit min. max. min. max. t pd_pal propagation delay time, input (or feedback node) to output through pal 2 10 2 12 ns t pd_pla propagation delay time, input (or feedback node) to output through pal + pla 3 12.5 3 15 ns t co clock to out (global synchronous clock from pin) 2 9 2 11 ns t su_pal setup time (from input or feedback node) through pal 8 10.5 ns t su_pla setup time (from input or feedback node) through pal + pla 10.5 13.5 ns t h hold time 00ns t ch clock high time 4 5 ns t cl clock low time 4 5 ns t r input rise time 20 20 ns t f input fall time 20 20 ns f max1 maximum ff toggle rate 2 (1/t ch + t cl )125100mhz f max2 maximum internal frequency 2 (1/t supal + t cf )64.550mhz f max3 maximum external frequency 2 (1/t supal + t co )58.847mhz t buf output buffer delay time 1.5 1.5 ns t pdf_pal input (or feedback node) to internal feedback node delay time through pal 8 10.5 ns t pdf_pla input (or feedback node) to internal feedback node delay time through pal + pla 10.5 13.5 ns t cf clock to internal feedback delay time 7.5 9.5 ns t init delay from valid v cc to valid reset 50 50 s t er input to output disable 3 16 19 ns t ea input to output valid 16 19 ns t rp input to register preset 17 20 ns t rr input to register reset 20 23 ns notes: 1. specifications measured with one output switching. see figure 6 and table 2 for derating. 2. this parameter guaranteed by design and characterization, not by test. 3. output c l = 5 pf. xcr3032.fm page 11 monday, october 9, 2000 6:44 pm
r xcr3032: 32 macrocell cpld ds038 (v1.3) october 9, 2000 www.xilinx.com 12 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. switching characteristics the test load circuit and load values for the ac electrical characteristics are illustrated below. v cc v in v out c1 r1 r2 s1 s2 component values r1 390 ? r2 390 ? c1 35 pf measurement s1 s2 t pzh open closed t pzl closed closed t p closed closed sp00477 note: for t phz and t plz c = 5 pf, and 3-state levels are measured 0.5v from steady-state active level. figure 6: t pd_pal vs. output switching v cc = 3.3v, 25 c ns 9.50 8.50 7.50 6.50 5.50 4.50 12 4 8 12 16 typical sp00449a figure 7: voltage waveform table 2: t pd_pal vs # of outputs switching (v cc = 3.3 v, t = 25 c) # of outputs 1 2 4 8 12 16 typical (ns) 6.2 6.4 6.6 6.9 7.2 7.5 90% 10% 1.5ns 1.5ns +3.0v 0v t r t f measurements: all circuit delays are measured at the +1.5v level of inputs and outputs, unless otherwise specified. input pulses sp00368 xcr3032.fm page 12 monday, october 9, 2000 6:44 pm
r xcr3032: 32 macrocell cpld 13 www.xilinx.com ds038 (v1.3) october 9, 2000 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. pin function and layout xcr3032 i/o pins xcr3032 global, power, and ground pins (1) global 3-state pin facilitates bed of nails testing without using logic resources. xcr3032 - 44-pin plcc xcr3032 - 44-pin vqfp function block macrocell pc44 vq44 notes 11442 12543 13644 1471 1582 1693 17115 18126 19137 110148 1111610 1121711 1131812 1141913 1152014 1162115 214135 224034 233933 243832 253731 263630 273428 283327 293226 2103125 2112923 2122822 2132721 2142620 2152519 2162418 pin type pc44 vq44 notes in0 43 37 in1 1 39 in2 44 38 in3 2 40 gtsn 44 38 (1) clk0 43 37 clk1 4 42 vcc 3, 15, 23, 35 9, 17, 29, 41 gnd 10, 22, 30, 42 4, 16, 24, 36 1 6 7 17 18 28 29 39 40 plcc sp00420a 44 1 11 12 22 23 33 34 tqfp sp00433a xcr3032.fm page 13 monday, october 9, 2000 6:44 pm
r xcr3032: 32 macrocell cpld ds038 (v1.3) october 9, 2000 www.xilinx.com 14 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/ pdn0007.htm for details. ordering information revision history component availability pins 44 type plastic vqfp plastic plcc code vq44 pc44 xcr3032 -12 c, i c, i -10 c, i c, i -8 c c example: xcr3032 -8 pc 44 c temperature range number of pins package type speed options -12: 12 ns pin-to-pin delay -10: 10 ns pin-to-pin delay -8: 8 ns pin-to-pin delay temperature range c = commercial, t a = 0 c to +70 c i = industrial, t a = ? 40 c to +85 c packaging options vq44: 44-pin vqfp pc44: 44-pin plcc device type speed options date version # revision 8/4/99 1.0 initial xilinx release. 2/7/00 1.1 converted to xilinx format and updated 8/10/00 1.2 updated pinout table and features. 10/09/00 1.3 added discontinuation notice. xcr3032.fm page 14 monday, october 9, 2000 6:44 pm

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